1. Field of the Invention
The present invention relates to a latch circuit for latching complementary signals that rise and fall oppositely to each other and an arithmetic unit employing the latch circuit.
2. Description of the Prior Art
FIG. 1 shows a latch circuit employing clock-controlled inverters according to a prior art, and FIG. 2 shows a latch circuit employing CMOS transmission gates according to another prior art.
In FIG. 1, the latch circuit consists of a clock-controlled inverter 11, an inverter 12, a clock-inverter 13, and an inverter 14. The inverter 11 is connected to an input terminal D. The inverter 12 has an input terminal connected to an output terminal of the inverter 11. The inverter 13 has an input terminal connected to an output terminal of the inverter 12 and an output terminal connected to the output terminal of the inverter 11. The inverter 14 has an input terminal connected to the output terminals of the inverters 11 and 13. The inverter 11 inverts and transmits an input signal when a clock signal .phi. is low level and an inverted clock signal .phi. is high level. The inverted clock signal .phi. is an inversion of the clock signal .phi..
The clock-controlled inverter 13 inverts and transmits the output of the inverter 12 when the clock signal .phi. is high level and the inverted clock signal .phi. is low level.
In FIG. 2, the latch circuit consists of CMOS transmission gates 25 and 28 and inverters 12, 14, and 27. The gate 25 is connected to an input terminal D. The inverter 12 has an input terminal connected to an output terminal of the transmission gate 25. The inverter 27 has an input terminal connected to an output terminal of the inverter 12. The transmission gate 28 has an input terminal connected to an output terminal of the inverter 27 and an output terminal connected to the output terminal of the transmission gate 25. The inverter 14 has an input terminal connected to the output terminals of the transmission gates 25 and 28. The transmission gate 25 transmits an input signal when a clock signal .phi. is low level and an inverted clock signal .phi. is high level. The transmission gate 28 transmits a signal when the clock signal .phi. is high level and the inverted clock signal .phi. is low level.
In the latch circuit shown in FIG. 1, the clock-controlled inverter 11 arranged in a first stage becomes conductive if the clock signal .phi. is low level and the inverted clock signal .phi. is high level, to fetch an input signal supplied to the input terminal D and transfer the same to an output terminal Q. In the latch circuit shown in FIG. 2, the CMOS transmission gate 25 arranged in a first stage becomes conductive if the clock signal .phi. is low level and the inverted clock signal .phi. is high level, to fetch an input signal supplied to the input terminal D and transfer the inverted signal D to an output terminal Q. Thereafter, when the clock signal .phi. changes to high level and the inverted clock signal .phi. to low level, the inverter 11 or the transmission gate 25 is turned off, while closing a circuit for holding the current output, i.e., the fetched input signal, which is, therefore, not affected by any change in an input signal. The current output is held as it is until the clock signal .phi. again changes to low level and the inverted clock signal .phi. to high level.
These latch circuits may receive, for example, output signals of a selector circuit of FIG. 3. The selector circuit has input terminals D1 and D2 for receiving input signals D1 and D2 and input terminals D1 and D2 for receiving inverted input signals D1 and D2. The selector circuit consists of nMOS transmission gates 31 to 34. The transmission gate 31 has a source terminal connected to the input terminal D1 and a gate terminal to receive a control signal A. The transmission gate 32 has a source terminal connected to the input terminal D2, a gate terminal to receive an inverted control signal A, which is an inversion of the control signal A, and a drain terminal connected to a drain terminal of the gate 31. The transmission gate 33 has a source terminal connected to the input terminal D1 and a gate terminal to receive the control signal A. The transmission gate 34 has a source terminal connected to the input terminal D2, a gate terminal to receive the inverted control signal A, and a drain terminal connected to a drain terminal of the gate 33. The selector circuit further has pMOS transistors 35 and 36. The transistor 35 has a gate terminal connected to the drain terminals of the transmission gates 33 and 34, a source terminal connected to a power supply for supplying a high level potential, and a drain terminal connected to an output terminal OUT. The transistor 36 has a gate terminal connected to the drain terminals of the transmission gates 31 and 32, a source terminal connected to the power supply, and a drain terminal connected to an output terminal OUT. The output terminal OUT provides a signal which is an inversion of an output signal provided by the output terminal OUT.
The operation of the selector circuit of FIG. 3 will be explained. If the control signal A is high level and the inverted control signal A is low level, the transmission gates 31 and 33 are conductive, and the transmission gates 32 and 34 are in the OFF state. As a result, the input terminals D2 and D2 are disconnected from the output terminals OUT and OUT and become irrelevant to them. Under this state, if the input terminal D1 is high level, the drain terminal of the transmission gate 31 provides a signal which is equal to the high level potential minus the gate threshold voltage Vth thereof. On the other hand, the input terminal D1 is low level, and therefore, the drain terminal of the transmission gate 33 quickly transmits the low level signal to the output terminal OUT. When the output terminal OUT becomes low level, the transistor 35 becomes conductive, to connect the drain terminal of the gate 31, i.e., the output terminal OUT to the power supply. As a result, the output terminal OUT receives the high level potential of the power supply compensating voltage drop due to the gate threshold voltage Vth.
If the input terminal D1 is low level, the input terminal D1 is high level, to achieve an operation opposite to the one mentioned above. Namely, the drain terminal of the transmission gate 31 quickly transmits the low level signal to the output terminal OUT, and the transmission gate 33 transmits a signal equal to the high level minus the gate threshold voltage Vth. The output terminal OUT is low level to turn on the transistor 36 to connect the power supply to the output terminal OUT. As a result, the output terminal OUT correctly provides the high level potential compensating the voltage drop due to the gate threshold voltage Vth.
If the control signal A is low level and the inverted control signal A is high level, the transmission gates 32 and 34 become conductive contrary to the above-mentioned case, and the pMOS transistors 35 and 36 help to provide a high-level output.
In the above operation, the high level is accomplished with aids of the transistor 35 or 36, while the low level is transmitted directly to any one of the output terminals OUT and OUT. Hence the transition to low level is always faster than the transition to the high level. Namely, as shown in the timing chart of FIG. 4, the completion of a rise in the output OUT is always behind the completion of a corresponding fall in the output OUT, and the completion of a rise in the output OUT is always behind the completion of a corresponding fall in the output OUT.
As explained above, the selector circuit of FIG. 3 provides complementary signals having the relationship of FIG. 4. It is usual that one of corresponding rise and fall in complementary output pulses is behind the other. If the output OUT of the complementary outputs of FIG. 4 is connected to the input terminal D of any one of the latch circuits of FIGS. 1 and 2, the latch circuit operates at high speed when the output OUT falls and slowly when the output OUT rises. To latch such signal having different rising time and falling time, the latch circuit must adjust itself to the slower timing. This hinders a high-speed latching operation even if the latch circuit is capable of speedily operating on one of the rise and fall of an input signal.